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p-to220-7-11 (p-to220-7-1) p-to263-7-1 (p-to220-7-8) p-to220-7-12 (p-to220-7-2) 5-v low-drop fixed voltage regulator tle 4271 semiconductor group 1 1998-11-01 features ? output voltage tolerance 2% ? low-drop voltage ? integrated overtemperature protection ? reverse polarity protection ? input voltage up to 42 v ? overvoltage protection up to 65 v ( 400 ms) ? short-circuit proof ? suitable for use in automotive electronics ? wide temperature range ? adjustable reset and watchdog time t not for new design type ordering code package tle 4271 q67000-a9210-a901 p-to220-7-11 tle 4271 s q67000-a9244-a901 p-to220-7-12 tle 4271 g q67006-a9195-a901 p-to263-7-1 t tle 4271 q67000-a9210-c801 p-to220-7-1 t tle 4271 s q67000-a9244-a801 p-to220-7-2 t tle 4271 g q67006-a9195-a801 p-to220-7-8 functional description this device is a 5-v low-drop fixed-voltage regulator. the maximum input voltage is 42 v (65 v, 400 ms). up to an input voltage of 26 v and for an output current up to 550 ma it regulates the output voltage within a 2 % accuracy. the short circuit protection limits the output current of more than 650 ma. the ic can be switched off via the inhibit input. an integrated watchdog monitors the connected controller. the device incorporates overvoltage protection and temperature protection that disables the circuit at unpermissibly high temperatures.
tle 4271 semiconductor group 2 1998-11-01 pin configuration (top view) figure 1 pin definitions and functions pin symbol function 1 i input ; block to ground directly on the ic with ceramic capacitor. 2inh inhibit 3ro reset output ; the open collector output is connected to the 5 v output via an integrated resistor of 30 k w. 4gnd ground 5d reset delay ; connect a capacitor to ground for delay time adjustment. 6w watchdog input 7q 5-v output ; block to ground with 22 m f capacitor, esr < 3 w . p-to220-7-11 (p-to220-7-1) p-to263-7-1 (p-to220-7-8) aep01939 gnd inh i ro w d q 17 aep01938 inh ro gnd 17 w d i q p-to220-7-12 (p-to220-7-2) gnd inh i ro 1 w aep02017 d q 7
tle 4271 semiconductor group 3 1998-11-01 application description the ic regulates an input voltage in the range of 5.5 v < v i < 36 v to v qnom = 5.0 v. up to 26 v it produces a regulated output current of more than 550 ma. above 26 v the save-operating-area protection allows operation up to 36 v with a regulated output current of more than 300 ma. overvoltage protection limits operation at 42 v. the overvoltage protection hysteresis restores operation if the input voltage has dropped below 36 v. the ic can be switched off via the inhibit input, which causes the quiescent current to drop below 50 m a. a reset signal is generated for an output voltage of v q < 4.5 v. the watchdog circuit monitors a connected controller. if there is no positive- going edge at the watchdog input within a fixed time, the reset output is set to low. the delay for power-on reset and the maximum permitted watchdog-pulse period can be set externally with a capacitor. design notes for external components an input capacitor c i is necessary for compensation of line influences. the resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 w in series with c i . an output capacitor c q is necessary for the stability of the regulating circuit. stability is guaranteed at values of c q 3 22 m f and an esr of <3 w . circuit description the control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of a series transistor via a buffer. saturation control as a function of the load current prevents any over-saturation of the power element. if the output voltage decreases below 4.5 v, an external capacitor c d on pin 4 (d) will be discharged by the reset generator. if the voltage on this capacitor v d drops below v drl , a reset signal is generated on pin 2 (ro), i.e. reset output is set low. if the output voltage rises above 4.5 v, c d will be charged with constant current. after the power-on-reset time v d reaches v du and the reset output will be set high again. the value of the power-on- reset time can be set within a wide range depending on the capacity of c d . the value of the pull-up resistor at reset output is typically 30 k w . after v d has reached the voltage v du and reset was set to high, the watchdog circuit is enabled and discharges c d with a constant current. if there is no positive-going edge observed at watchdog input, c d will be discharged down to v dwl . then reset will be set low and the watchdog circuit will be disabled. c d will be charged with the current as at power-on reset until v d reaches v du and reset will be set high again. if a watchdog pulse will be observed before c d is discharged down to v dwl , the watchdog circuit will be enabled and c d will be charged too, but reset will not be set low. after v d has reached v du , the periodical behavior starts again.
tle 4271 semiconductor group 4 1998-11-01 the ic also incorporates a number of internal circuits for protection against: ? overload ? overvoltage ? overtemperature ? reverse polarity figure 2 block diagram temperature sensor saturation control and protection circuit + - reference bandgap adjustment reset generator watchdog 4 2 1 7 3 5 6 inh gnd w aeb01940 control amplifier buffer i q d r
tle 4271 semiconductor group 5 1998-11-01 absolute maximum ratings t j = C 40 to 150 c parameter symbol limit values unit notes min. max. input voltage voltage current v i v i i i C 42 C C 42 65 C v v ma C t 400 ms internally limited inhibit voltage voltage current v e v e i e C 42 C C 42 65 C v v ma C t 400 ms internally limited reset output voltage current v r i r C 0.3 C 42 C v ma C internally limited reset delay voltage current v d i d C 0.3 C 5 7 5 v ma C C watchdog voltage current v w i w C 0.3 C 5 7 5 v ma C C output voltage current v q i q C 1.0 C 5 16 C v ma C internally limited ground current i gnd C 0.5 C a C temperatures junction temperature storage temperature t j t stg C C 50 150 150 c c C C
tle 4271 semiconductor group 6 1998-11-01 optimum reliability and life time are guaranteed if the junction temperature does not exceed 125 c in operating mode. operation at up to the maximum junction temperature of 150 c is possible in principle. note, however, that operation at the maximum permitted ratings could affect the reliability of the device. operating range parameter symbol limit values unit notes min. max. input voltage v i 640v C junction temperature t j C 40 150 cC thermal resistance junction ambient r thja C65 70 k/w k/w C smd version junction case r thjc z thjc C C C 3 6 2 k/w k/w k/w C p-to220-7-8 t < 1ms
tle 4271 semiconductor group 7 1998-11-01 characteristics v i = 13.5 v; C 40 c t j = 125 c (unless otherwise specified) parameter symbol limit values unit test condition min. typ. max. output voltage v q 4.90 5.00 5.10 v 5 ma i q 550 ma; 6 v v i 26 v output voltage v q 4.90 5.00 5.10 v 26 v v i 36 v; i q 300 ma; output current limiting i qmax 650 800 C ma v q = 0 v current consumption i q = i i i q CC50 m a v e = 0 v; i q = 0 ma current consumption i q = i i i q C 800 C m a v e = 5 v; i q = 0 ma current consumption i q = i i C i q i q C11.5ma i q = 5 ma current consumption i q = i i C i q i q C5575ma i q = 550 ma current consumption i q = i i C i q i q C7090ma i q = 550 ma; v i = 5 v drop voltage v dr C 350 700 mv i q = 550 ma 1) load regulation d v q C2550mv i q = 5 to 550 ma; v i = 6 v supply voltage regulation d v q C1225mv v i = 6 to 26 v i q = 5 ma power supply ripple rejection psrr C54Cdb f r =100hz; v r =0.5 v ss 1) drop voltage = v i C v q (measured when the output voltage has dropped 100 mv from the nominal value obtained at 13.5 v input)
tle 4271 semiconductor group 8 1998-11-01 reset generator switching threshold v rt 4.5 4.65 4.8 v C reset high voltage v roh 4.5 C C v C reset low voltage v rol C60Cmv r intern =30 k w 2) ; 1.0 v v q 4.5 v reset low voltage v rol C 200 400 mv i r = 3 ma, v q = 4.4 v reset pull-up r 18 30 46 k w internally connection to q3 lower reset timing threshold v drl 0.2 0.45 0.8 v v q < v rt charge current i d 81425 m a v d = 1.0 v upper timing threshold v du 1.4 1.8 2.3 v C delay time t d 81318ms c d = 100 nf reset reaction time t rr CC3 m s c d = 100 nf overvoltage protection turn-off voltage v i , ov 40 44 46 v C inhibit inhibit on voltage v inh 1.0 2.0 3.5 v v q = high (> 4.5 v) inhibit off voltage v inh 0.8 1.3 3.3 v v q = low (< 0.8 v) inhibit current i inh 81225 m a v inh = 5 v watchdog upper timing threshold v du 1.4 1.8 2.3 v C lower watchdog timing threshold v dwl 0.2 0.45 0.8 v C discharge current i dis 1.5 2.7 3.5 m a v d = 1 v characteristics (contd) v i = 13.5 v; C 40 c t j = 125 c (unless otherwise specified) parameter symbol limit values unit test condition min. typ. max.
tle 4271 semiconductor group 9 1998-11-01 charge current i d 81425 m a v d = 1 v watchdog period t w 40 55 75 ms c d = 100 nf watchdog trigger time t wt 30 45 66 ms c d = 100 nf see diagram watchdog pulse slew rate v w 5 CCv/ m s from 20% to 80% v q 2) reset peak is always lower than 1.0 v. characteristics (contd) v i = 13.5 v; C 40 c t j = 125 c (unless otherwise specified) parameter symbol limit values unit test condition min. typ. max.
tle 4271 semiconductor group 10 1998-11-01 figure 3 test circuit figure 4 application circuit 3 2 v v i v inh i c d i d 5 d 4 w gnd v 6 aes01941 r v v q 470 nf 1000 f i m i i tle 4271 17 q 22 f r m i 22 f to mc reset 3 4 5 100 nf aes01942 m 470 nf input tle 4271 1 7 5 v-output 6 2 e.g. kl 15 input
tle 4271 semiconductor group 11 1998-11-01 figure 5 time response figure 6 time response, watchdog behavior aes01927 d = d i d v d c t < t rr rr t t d d v v q v i v r v rt v drl du v power-on-reset thermal shutdown at input voltage drop undervoltage spike secondary load bounce aes01943 w t t wr d v v q v i v r v dwl du v w v w t du v = - v dwl ( ) ( ) i dis + i d i d x dis ii wr t v = du - d dwl v c d d c = (watchdog reset time) t i = wt v du dis v - dwl c d wt t
tle 4271 semiconductor group 12 1998-11-01 output voltage v q versus temperature t j output current i q versus temperature t j output voltage v q versus input voltage v i ( v i = v e ) output current i q versus input voltage v i 4.90 4.80 4.70 40 -40 0 4.60 5.00 v 5.20 5.10 q 160 c 80 120 t j aed01928 v i = 13.5 v v 600 400 200 40 -40 0 0 800 ma 1200 1000 q i 160 c 80 120 t j aed01930 r 6 4 2 0 4 0 2 8 12 10 q v v 10 v 68 v i aed01929 = 25 l w 0.6 0.4 0.2 20 010 0 0.8 a 1.2 1.0 q i = 25 c t j 50 v 30 40 v i aed01931 = 125 c t j
tle 4271 semiconductor group 13 1998-11-01 current consumption i q versus output current i q current consumption i q versus input voltage v i current consumption i q versus output current i q drop voltage v dr versus output current i q 0 0 20 120 60 40 i q ma aed01932 80 ma 1 2 3 4 5 6 q i v i = 13.5 v 60 40 20 20 010 0 80 ma 120 100 q i 50 v 30 40 v i aed01934 = 20 r l w l r = 50 r = 10 l w w 300 40 30 100 0 200 0 10 20 80 60 70 50 ma q i v = 13.5 v i ma 400 600 i q aed01933 400 200 300 100 200 0 400 0 800 600 700 500 dr v mv ma 600 1000 i q aed01935 t = 125 c j t =25 j c
tle 4271 semiconductor group 14 1998-11-01 inhibit current i e versus inhibit voltage v e inhibit current consumptions i e versus temperature t j output voltage v q versus inhibit voltage v e inhibit voltages v e versus temperature t j 0 0 1 6 3 2 e aed01944 4 v 2 4 6 8 10 12 v i = 13.5 v = 25 c j t e, high i i e, on i e, off 5 e v m a i -40 0 0 120 80 40 t j a 14 aed01946 160 i e m 2 4 6 8 10 12 i e, high i e, on i e, off 3 3 2 1 0 0 1 2 6 5 4 v 5 v 4 6 v e = 25 c = 13.5 v i j v t aed01945 q v 3 2 1 40 -40 0 0 4 v 6 5 e 160 c 80 120 aed01947 j t v v e, on e, off v
tle 4271 semiconductor group 15 1998-11-01 switching voltage v du and v dwl versus temperature t j watchdog pulse time t w versus temperature t j charge current i d and discharge current i dis versus temperature t j du 40 -40 0 0 v v v v i 160 c 80 120 t j aed01948 = 13.5 v 1.2 0.8 0.4 1.6 2.4 2.0 dwl v 80 40 -40 0 10 30 20 40 0 50 60 70 80 160 120 c t j = 13.5 v aed01950 i c d v = 100 nf ms w t 80 8 -40 8 2 6 4 40 0 i d a 10 12 i m 14 16 160 120 c t j = 13.5 v aed01949 i v d v = 1 v dis i
tle 4271 semiconductor group 16 1998-11-01 package outlines 10 +0.4 3.75 +0.1 17 1.27 0.6 8.4 0.4 0.4 4.5 0.4 +0.1 10.2 15.4 0.3 8.8 -0.2 16 1.27 +0.1 +0.1 2.8 4.6 -0.2 2.6 8.6 0.3 0.3 0.4 19.5 max 1 x 45? at dam bar (max 1.8 from body) im dichtstegbereich (max 1.8 vom k?rper) -0.15 -0.15 m 0.6 7x -0.2 10.2 1) 1) 0.75 1) 0.75 gpt05108 p-to220-7-1 (plastic transistor single outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tle 4271 semiconductor group 17 1998-11-01 0.4 +0.1 2.6 11 13 10.2 3.75 +0.1 +0.4 10 -0.2 2.8 1.27 17 7x m 0.6 +0.1 0.6 1) -0.15 -0.15 1) 0.75 1) 0.75 im dichtstegbereich (max 1.8 vom k?rper) at dam bar (max 1.8 from body) 1.27 +0.1 4.6 1 x 45? -0.2 8.8 -0.2 15.4 p-to220-7-2 (plastic transistor single outline package) gpt05257 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tle 4271 semiconductor group 18 1998-11-01 gpt09083 typical 0.1 1.27 4.4 9.25 0.2 0.05 1) all metal surfaces tin plated, except area of cut. c 2.4 0.5 0.1 0.3 8.6 10.2 0.3 0.4 3.9 0.4 8.4 3.7 0.3 a a 0.25 m 9.8 0.15 2.8 1) 15.65 0.3 13.4 0...0.15 1.27 0.6 0.1 c 0.2 17 0.3 8.5 1) 10 0.2 3.7 -0.15 7x p-to220-7-11 (plastic transistor single outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tle 4271 semiconductor group 19 1998-11-01 gpt09084 a b a 0.25 m typical 9.8 0.15 2.8 1) 15.65 0.3 13.4 0...0.15 1.27 0.6 0.1 0.1 1.27 4.4 b 9.25 0.2 0.05 1) all metal surfaces tin plated, except area of cut. c 0.2 17 0.3 8.5 1) 10 0.2 3.7 -0.15 c 2.4 0.5 0.1 13 0.5 0.5 11 7x p-to220-7-12 (plastic transistor single outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tle 4271 semiconductor group 20 1998-11-01 a 8? max. b a 0.25 m 0.1 typical 9.8 0.15 0.2 10 8.5 1) 8 1) (15) 0.2 9.25 0.3 1 0...0.15 7x0.6 0.1 0.1 1.27 4.4 b 0.5 0.1 0.3 2.7 4.7 0.5 0.05 1) 0.1 all metal surfaces tin plated, except area of cut. 2.4 6x1.27 p-to263-7-1 (plastic transistor single outline package) gpt09114 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device gpt05874 10.2 8.0 10.1 0.6 6 x 1.27 = 7.62 3.5 0.4 8.8 1.5 0.2 1.27 2.6 4.6 1.27 1) 1) shear and punch direction burr free surface p-to220-7-8 (plastic transistor single outline package)

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